As the electronics industry approaches the physical limits of transistor density on traditional chips, the need for innovative solutions has become more urgent than ever. MIT engineers have introduced a groundbreaking method to construct “high-rise” 3D chips, stacking multiple layers of semiconductors without the constraints of bulky silicon wafers. This development could exponentially enhance computing power for AI hardware, making it faster, denser, and more efficient.
Moving Beyond Silicon
The semiconductor industry has long relied on silicon wafers as the foundation for chip production. However, these thick substrates hinder communication between layers in stacked designs. MIT’s new approach bypasses the need for silicon wafers, allowing semiconductor layers to be directly stacked while preserving the integrity of existing circuitry.
Using their novel method, the team fabricated multilayered chips with high-quality semiconducting materials, creating seamless integration between layers. This process enables transistors and memory elements to communicate more efficiently, paving the way for AI hardware that’s compact yet powerful enough to rival today’s supercomputers.
“This breakthrough opens up enormous potential for the semiconductor industry, allowing chips to be stacked without traditional limitations,” says Jeehwan Kim, associate professor of mechanical engineering at MIT. “It could lead to orders-of-magnitude improvements in computing power for applications in AI, logic, and memory.”
Edge-Seeding: A Cool Solution
A key innovation lies in the team’s ability to grow single-crystalline materials at low temperatures. Traditional methods required high heat (around 900°C), which would damage underlying circuitry. Inspired by metallurgical techniques, the researchers developed an “edge-seeding” approach to grow semiconductors at just 380°C.
By depositing seeds of transition-metal dichalcogenides (TMDs) at the edges of microscopic pockets, the team ensured the growth of single-crystalline layers at lower temperatures. TMDs, such as molybdenum disulfide and tungsten diselenide, offer excellent conductivity and are ideal candidates for fabricating high-performance transistors.
Toward the Future of AI Chips
The researchers used this method to build multilayered chips containing alternating layers of n-type and p-type transistors—essential components of modern logic circuits. Unlike conventional 3D chips, which rely on drilled silicon wafers for stacking, MIT’s design eliminates intermediate barriers, doubling the density of semiconducting elements.
The potential applications are vast. These stackable chips could power AI systems for laptops, wearable devices, and even data centers, offering unparalleled speed and storage capabilities.
“A product realized by our technique is not only a 3D logic chip but also 3D memory and their combinations,” Kim explains. “With our growth-based monolithic 3D method, you could grow tens to hundreds of logic and memory layers, right on top of each other.”
From Lab to Industry
To bring this technology to market, Kim has co-founded FS2 (Future Semiconductor 2D materials). The company is now working to scale up production and demonstrate professional AI chip operations.
This innovation marks a significant milestone in the evolution of semiconductor technology. By breaking free from traditional silicon-based constraints, MIT’s high-rise 3D chips could redefine the future of computing, enabling next-generation AI applications to flourish.
Source: https://news.mit.edu/2024/mit-engineers-grow-high-rise-3d-chips-1218
